This invention relates generally to a buffer system and more particularly to a system for use with serial data/parallel data converters. Still more particularly, the invention relates to a system for use with serial data/parallel data converters adapted for use in Fibre Channel systems.
As is known in the art, serial data/parallel data converters have a wide variety of applications. One such application is with Fibre Channel systems. For example, in one arrangement, data passes between a central processing system and a bank of magnetic data storage disks through the Fibre Channel system. More particularly, the bank of magnetic storage disks is coupled to central processing units through an interface. The interface includes CPU, or "front end", controllers and "back end" disk controllers. The interface may also include, in addition to the controllers, a semiconductor temporary memory storage or cache, as described in U.S. Pat. No. 5,206,939, entitled "System and Method for Disk Mapping and Data Retrieval", inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
While data passes serially to, and from, the interface via the Fibre Channels; data passes in parallel through the interface itself. Therefore, the "front end" and "back end" controllers must include a serial data/parallel data converter to convert the serial data fed to the controller by the Fibre Channel into parallel, multi-bit data, on the one hand, and to convert the parallel data produced by the controller into single bit, serial data for the Fibre Channel. One such serial data/parallel data converter is sometimes referred to as a gigabit link module (GLM). These GLM's are available in full, 1.062 gigabit per second Fibre Channel speed; half speed and, quarter speed modules, as well as in 10 bit, 20 bit and 40 bit data widths. For each speed/data width configuration, however, a different controller configuration is required.